Andrew Copper


Electronics Engineer


Executive Summary

Proven manager and experienced digital design developer and designer, with significant knowledge of Design For Test and Static Timing Analysis, who is eager to learn new skills and meet new challenges. Self directed team player who adds both practical and organizational insight to his team. Works well with customers. Excellent presentation skills with extensive classroom teaching and demo experience.


  • Management of small to medium sized teams
  • Budget focused, and able to find practical solutions to problems
  • Numerous scripting languages, Perl, C++/C, Visual Basic, Assembly Language
  • Full project life-cycle experience
  • Writing, editing, technical reviewer
  • Technical training and presentation
  • ITC program committee and paper reviewer from 2000 to present
  • SNUG Technical Committee San Jose 2000- to present, and Boston 2001 to present

Tools Summary

Synopsys : Design Compiler, Physical Compiler, DFT Compiler, BSD Compiler, PrimeTime, VCS, TetraMAX, Deterministic BIST (DBIST), SoCBIST, SoCTEST
Mentor : FastScan, FlexTest, DFTAdvisor, BSDArchitect, Modelsim
LogicVision : LogicBIST, IC MemoryBIST
Cadence : VerilogXL, NCVerilog

Career Summary

  • Director Test Technology - E L & Associates, Inc.
  • President - Folsom Street Events
  • Staff Applications Engineer / Applications Manager - Azuro, Inc.
  • Senior Corporate Applications Engineer - Synopsys, Inc.
  • Senior Engineer - Texas Instruments, Inc.
  • Design Engineer - Oasix, Inc. (acquired by TI)
  • Development Engineer - Two Way TV Ltd.
  • Development Engineer - Switched Reluctance Drives Ltd.



Pleasanton, CA
EL & Associates

Director Test Technology

Director of the engineering team specializing in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. Engaged with customers from the RTL phase to silicon prototype.

Specialized in design-for-test, crisis management, project management, as well as DFT compression technologies. PrimeTime static timing analysis as well as complete methodology flows are also a key focus. Proven success on 90nm 40 million plus gate designs, using Transition Delay Fault (TDF) testing, as well as Critical Path Analysis (CPA).


San Francisco, CA
Folsom Street Events

Board President and Event Manager

Board President of an extremely active working board for a non-profit organization producing events from 2000 people to 400,000 people. Directly manage a staff of 2, board of 10, associate board of 9 and volunteer base of 450. Overall responsible for the budget of $500,000 and complete event management. Grown the ability to produce these quality events, enabled the organization to employ a full time staff, and consistently give away large sums of money to local charities ($285,000 last year).


San Jose, CA
Azuro, Inc.

Staff Applications Engineer / Applications Manager

Led the applications team of 3 for this start-up EDA company, developing an innovative low power technology using physical information.

  • Worked with the R&D team to specify and develop new functionality.
  • Provided front line customer support, training and presentations.
  • Coordinated the entire effort to have a suite at DAC 2004.
  • General technical go to for all networking, phone, office and computer problems.


Mountain View, CA
Synopsys, Inc.

Senior Corporate Applications Engineer

Member of the CAE team supporting the Synopsys DFT tools.

  • Using input from marketing and R&D, designed and created product demos, which I then presented at DAC, SNUG, and ITC.
  • Created the internal and external training on all DFT product tools: DFT Compiler, TetraMAX, SoCBIST, SoCTEST, and Physical Scan Synthesis.
  • Key contributor to the flagship SoCBIST product launch team; providing targeted on-site support, customer and AC training, and significant customer integration assistance.
  • Developed flow and methodology for physical scan synthesis, and became the point person for that tool.


San Jose, CA
Texas Instruments Inc.

Senior Engineer / Member Group Technical Staff

Expert in both Mentor & Synopsys tools and flows. Acted as key contact in these areas, to advise on numerous designs. Specific accomplishments included:

  • Architected and implemented complete synthesis, static timing, scan and ATPG flows. This included cost analyses for various DFT alternatives and fault coverage analyses.
  • Worked extensively with customers and with internal TI engineers
  • Provided individual mentoring and developed a central lessons-learned web site
  • Interacted independently with large customers with minimal assistance
  • Influence the move to more efficient test methods, helping reduce time to market and total cost of test
  • Performed crisis management for complex ASICs with large DFT problems
  • Solve problems with RTL and clock tree structures
  • Developed complete training programs in general IC testability concepts and for tool-specific flows
  • Member, Technical Program Committee for Texas Instruments Symposium on Test (TIST); presented several publications
  • Elected to Member Group Technical Staff (MGTS), TI Technical Ladder


London, UK
Two Way TV, Ltd.

Development Engineer

Part of the hardware engineering team, developing a set-top box for interactive TV programming

  • Working alone, I designed an ASIC to significantly reduce the cost of the handset for the interactive TV home unit
  • Two International Patents awarded: Handset Multiplexing, and Handset Time Stamping


Leeds, UK
Switched Reluctance Drives, Ltd.

Development Engineer

Part of the hardware engineering team, developing high power drives and machinery

  • Experience in digital design from concept to silicon. Involved design, simulation, and production of synthesis and production vectors. Produced 'Right First Time Silicon'. FPGAs used for emulation
  • International Patent awarded: Rotor Position Sensing (sole inventor)


B.Eng. (Hons) Electronic and Electrical Engineering
School of Electronic and Electrical Engineering, Leeds University.
Major: Power Electronics and Drives. Dissertation - Construction of a GPS receiver.


References are available upon request.
58 Caselli Ave
San Francisco,  CA  94114-2319

© 2006, Andrew Copper